Interactive study hub · Dr. Surekha Lanka

Latches &
Flip-Flops

A one-bit memory lab for understanding level-sensitive latches, clock-edge flip-flops, and the rules that keep sequential circuits predictable.

24 slides covered8-question checkpointState explorers
01 / foundation

Core concepts

Sequential circuits combine logic with storage: current outputs can depend on current inputs and values held from before.

01 — MEMORY

One bit, held

Latches and flip-flops store either 0 or 1. They are building blocks of sequential circuits, registers, and computer memory systems.

02 — LATCH

Level-sensitive

With enable active, the output can follow the input. When enable becomes inactive, it keeps its last value. Latches have no clock pulse and support asynchronous sequential circuits.

03 — FLIP-FLOP

Edge-triggered

It reads at a rising or falling clock edge, then holds its value until the next active edge. Correction: flip-flops are normally used in synchronous clocked systems.

02 / timing contrast

Latch vs. flip-flop

Latch ▱

TriggerSignal level / enable
TransparencyInput may pass through while enabled
TimingNo clock pulse
Typical roleAsynchronous sequential circuits

Flip-flop ↟

TriggerClock transition (edge)
SamplingOnly at the active edge
TimingClock pulse
Typical roleSynchronous clocked systems
03 / devices

Four memory devices

Select a card’s reveal to pair the logic rule with its real-world analogy or an exam-ready distinction.

SR LATCH

Set / Reset

SR latch using NAND gates

Fundamental static-gate latch; S and R mean set and reset. It can be made with two cross-coupled NOR or NAND gates.

Room light: SET turns the light ON; RESET turns it OFF. Both pressed together is the invalid state.
D LATCH

Data latch

D latch logic symbol

D latch avoids the SR invalid state: its inputs are complements. D means “data” and stores one bit temporarily.

Phone screen lock: with enable E = 1, Q follows D; with E = 0, the stored screen state remains unchanged.
SR FLIP-FLOP

Clocked Set / Reset

S  R  ▸  Q

The simplest flip-flop, operating on positive or negative clock transitions—not an enable signal. It is constructed from a latch plus gating.

Emergency alarm: S is an emergency/fire button, R is authorized reset, clock is a system check pulse, and Q is alarm ON/OFF.
JK FLIP-FLOP

Clocked J / K

JK flip-flop logic symbol

A gated SR flip-flop whose clock input circuitry prevents the illegal condition when both inputs are logic 1.

Office attendance: J = Join/IN, K = Kick-out/OUT, clock = entry/exit detection pulse; Q marks inside (1) or outside (0).
04 / try the states

Truth-table explorer

Choose inputs and set the previous Q state. The table reacts using the standard active-high SR and JK rules.

INPUTS: S, R
NEXT STATE
Qₙ₊₁ = Qₙ

Hold: S = 0 and R = 0 preserves the previous stored bit.

05 / recall

Flip to learn

Six compact prompts. Tap/click each card, then explain the answer aloud before checking.

06 / self-marking checkpoint

Quiz lab

Choose an answer to lock it, reveal feedback, then continue. Your score updates as you go.

Question 1 of 8Score: 0 / 0

07 / source ledger

Slide coverage — 24 slides

The source progression is grouped below so every slide is represented, including repeated reinforcement and construction slides.

Slides 1–6 · Foundations

  • Title and instructor
  • Latch / flip-flop: one-bit memory
  • Level-sensitive latch and asynchronous use
  • Edge-triggered flip-flop and clock
  • Sequential circuit: logic + storage
  • Inputs, prior values, two storage types

Slides 7–12 · Latches

  • SR: fundamental static-gate building block
  • S / R = set / reset
  • NOR/NAND, recursive cross-coupling
  • Room-light SET/RESET analogy
  • Both buttons: invalid state
  • D latch inputs CLK and D

Slides 13–16 · D & SR FF

  • D latch avoids SR invalid state
  • Complemented inputs; D = data
  • Phone screen lock example
  • Four types: SR, D, JK, T

Slides 17–20 · SR FF

  • SR flip-flop: Set Reset, clocked
  • Positive/negative transitions vs enable
  • NOR-latch construction + two NAND gates
  • NAND-latch construction + two NAND gates

Slides 21–22 · Alarm & JK

  • Emergency alarm: S, R, clock, Q
  • JK: gated SR; avoids illegal 1/1 output
  • JK construction methods

Slides 23–24 · JK construction

  • NOR-latch-based JK construction
  • Office attendance IN/OUT system
  • NAND-latch-based JK construction
  • J,K both low: no state change
DIAGRAM ATTRIBUTION

Source URLs

The embedded diagrams are local copies of public-domain Wikimedia Commons drawings by jjbeard, selected to reinforce the Week 5 material:

Wikimedia Commons — SR latch symbol
Wikimedia Commons — D transparent latch symbol
Wikimedia Commons — JK flip-flop symbol